Location
Hyderabad
Job Type
Full-time
Posted
June 02, 2026
Job Description
Job Summary:
We are looking for a highly skilled
Full-Chip Static Timing Analysis (STA) Engineer
with 3–6 years of experience in VLSI Physical Design/Timing Closure. The candidate will be responsible for full-chip timing analysis, timing closure, constraint development, and optimization activities across multiple design stages.
Key Responsibilities:
Perform
full-chip Static Timing Analysis (STA)
and timing sign-off.
Develop and validate
SDC constraints .
Handle timing closure activities including setup, hold, recovery, and removal checks.
Analyze and resolve timing violations across different corners and modes.
Work on
MCMM (Multi-Corner Multi-Mode)
timing analysis.
Perform timing ECO implementation and validation.
Collaborate with Physical Design, CTS, PnR, DFT, and RTL teams.
Debug timing issues related to clock domains, false paths, and timing exceptions.
Generate timing reports and provi...
We are looking for a highly skilled
Full-Chip Static Timing Analysis (STA) Engineer
with 3–6 years of experience in VLSI Physical Design/Timing Closure. The candidate will be responsible for full-chip timing analysis, timing closure, constraint development, and optimization activities across multiple design stages.
Key Responsibilities:
Perform
full-chip Static Timing Analysis (STA)
and timing sign-off.
Develop and validate
SDC constraints .
Handle timing closure activities including setup, hold, recovery, and removal checks.
Analyze and resolve timing violations across different corners and modes.
Work on
MCMM (Multi-Corner Multi-Mode)
timing analysis.
Perform timing ECO implementation and validation.
Collaborate with Physical Design, CTS, PnR, DFT, and RTL teams.
Debug timing issues related to clock domains, false paths, and timing exceptions.
Generate timing reports and provi...