Hiring Senior DFT Engineers

Design for Test (DFT) Engineer / Senior DFT Engineer / Principal DFT Engineer

Experience: 5–25 Years

Location: Bangalore | Hyderabad | Ahmedabad

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we have a role that will challenge and grow your skills in advanced silicon testing.

Core Responsibilities

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery.

Key focus areas include:

• Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC.
• Block Level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization.