Lead ASIC Engineer: High-Performance Subsystems

570 Cisco Systems (Switzerland) GmbH in Thalwil, Switzerland, seeks an experienced ASIC design lead to define, design, and verify high-performance subsystems for Cisco platforms. You will oversee analog/mixed-signal architecture and collaborate with cross-functional teams to optimize power, performance, and area.

The role requires extensive experience with high-frequency CMOS design, Cadence Virtuoso, and scripting in Python/MATLAB/C. A strong publication or patent track is a plus.