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Platform Test Engineer ( L2/L3 Protocols| Routing| Python Automation (8-12 yrs))
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View JobPlatform Test Engineer ( L2/L3 Protocols| Routing| Python Automation (5-8 yrs) )
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View JobPlatform Test Engineer - L2/L3 Protocols| Routing| Python Automation (8-12 yrs)
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View JobASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore
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View JobASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)
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View JobASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore
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View JobASIC Engineering Analog Design Leader:ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 10+ years
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