Senior Design Verification Engineer

• Apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design.
• Work independently on various DV tasks and providing technical guidance to the DV team.
• Involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
• Perform USB‑IF compliance testing.

Requirements

• Strong coding with Verilog and SystemVerilog
• Good knowledge of design verification methodology UVM
• Strong experiences with sequence creation, functional cover groups and assertion coding
• Familiar with scripting language such as Perl, C shell, Makefile, Ruby
• Familiarity with industry-standard high-speed protocols – USB Technical Skills/Expertise:

a. USB 3.0, 3.1, 3.2, or USB4 protocols. <...