Senior Verification Engineer

Job Description: Position Summary The primary objective of this role is to develop and use verification environments to verify digital based products and contribute to the verification methodology development and project execution resulting in new and/or improved products. Main Responsibilities Define test plans Define and implement UVM based verification frameworks, code UVM components, tests and sequences and perform verification of digital and mixed-signal products Define and implement functional coverage Perform RTL and gate level simulations, analyze and debug simulation results and interact with design team Support validation of silicon Requirements Requirements/Qualifications: Mandatory Skills Proficiency in System Verilog Proficiency in UVM methodology Extensive experience in building digital verification frameworks from scratch, using UVM methodology Proficiency in System Verilog Assertions Must have good problem-solving skills Must have good communication skills and the abili...