Location
Austin
Job Type
Full-time
Posted
June 04, 2026
Job Description
Description
When a new Trainium or Inferentia chip comes back from the fab, our code is the first software to touch it. We're looking for a hands-on engineering manager who lives and breathes low-level software — someone who's debugged register-level issues at 3am and wants to build a team that does it better.
Our SoC HAL (Hardware Abstraction Layer) team owns the lowest layer of user-space software on AWS's custom ML accelerator chips: the firmware that boots, configures, and manages every hardware block on the SoC. Your software runs as a shared library on embedded Linux, reaching into the chip to program PCIe links, initialize HBM controllers, configure PLLs, manage interrupt controllers, and orchestrate fabric interconnects across 270+ hardware block instances per chip — all deployed across millions of servers in AWS's global fleet.
Tech stack: C++17, CMake, GoogleTest, Python, SystemVerilog DPI, SPI, APB/AXI bus protocols, PCIe, UCIe, HBM, PLL, custom IPs
...
When a new Trainium or Inferentia chip comes back from the fab, our code is the first software to touch it. We're looking for a hands-on engineering manager who lives and breathes low-level software — someone who's debugged register-level issues at 3am and wants to build a team that does it better.
Our SoC HAL (Hardware Abstraction Layer) team owns the lowest layer of user-space software on AWS's custom ML accelerator chips: the firmware that boots, configures, and manages every hardware block on the SoC. Your software runs as a shared library on embedded Linux, reaching into the chip to program PCIe links, initialize HBM controllers, configure PLLs, manage interrupt controllers, and orchestrate fabric interconnects across 270+ hardware block instances per chip — all deployed across millions of servers in AWS's global fleet.
Tech stack: C++17, CMake, GoogleTest, Python, SystemVerilog DPI, SPI, APB/AXI bus protocols, PCIe, UCIe, HBM, PLL, custom IPs
...
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